Messages in this thread Patch in this message | | | From | Mason Huo <> | Subject | [PATCH v2] irqchip/irq-sifive-plic: Add syscore callbacks for hibernation | Date | Thu, 9 Feb 2023 11:43:22 +0800 |
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The priority and enable registers of plic will be reset during hibernation power cycle in poweroff mode, add the syscore callbacks to save/restore those registers.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Reviewed-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> --- drivers/irqchip/irq-sifive-plic.c | 94 ++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index ff47bd0dec45..4683e49d90ad 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -17,6 +17,7 @@ #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/spinlock.h> +#include <linux/syscore_ops.h> #include <asm/smp.h> /* @@ -67,6 +68,8 @@ struct plic_priv { struct irq_domain *irqdomain; void __iomem *regs; unsigned long plic_quirks; + unsigned int nr_irqs; + unsigned long *priority_reg; }; struct plic_handler { @@ -78,11 +81,13 @@ struct plic_handler { */ raw_spinlock_t enable_lock; void __iomem *enable_base; + u32 *enable_reg; struct plic_priv *priv; }; static int plic_parent_irq __ro_after_init; static bool plic_cpuhp_setup_done __ro_after_init; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); +static struct plic_priv *priv_data; static int plic_irq_set_type(struct irq_data *d, unsigned int type); @@ -229,6 +234,68 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) return IRQ_SET_MASK_OK; } +static int plic_irq_suspend(void) +{ + unsigned int i, cpu; + u32 __iomem *reg; + + for (i = 0; i < priv_data->nr_irqs; i++) + if (readl(priv_data->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)) + __set_bit(i, priv_data->priority_reg); + else + __clear_bit(i, priv_data->priority_reg); + + for_each_cpu(cpu, cpu_present_mask) { + struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); + + if (!handler->present) + continue; + + raw_spin_lock(&handler->enable_lock); + for (i = 0; i < DIV_ROUND_UP(priv_data->nr_irqs, 32); i++) { + reg = handler->enable_base + i * sizeof(u32); + handler->enable_reg[i] = readl(reg); + } + raw_spin_unlock(&handler->enable_lock); + } + + return 0; +} + +static void plic_irq_resume(void) +{ + unsigned int i, cpu; + u32 __iomem *reg; + + for (i = 0; i < priv_data->nr_irqs; i++) + writel(test_bit(i, priv_data->priority_reg), + priv_data->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); + + for_each_cpu(cpu, cpu_present_mask) { + struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); + + if (!handler->present) + continue; + + raw_spin_lock(&handler->enable_lock); + for (i = 0; i < DIV_ROUND_UP(priv_data->nr_irqs, 32); i++) { + reg = handler->enable_base + i * sizeof(u32); + writel(handler->enable_reg[i], reg); + } + raw_spin_unlock(&handler->enable_lock); + } +} + +static struct syscore_ops plic_irq_syscore_ops = { + .suspend = plic_irq_suspend, + .resume = plic_irq_resume, +}; + +static void plic_irq_pm_init(void) +{ + register_syscore_ops(&plic_irq_syscore_ops); +} + static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { @@ -345,12 +412,14 @@ static int __init __plic_init(struct device_node *node, u32 nr_irqs; struct plic_priv *priv; struct plic_handler *handler; + unsigned int cpu; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->plic_quirks = plic_quirks; + priv_data = priv; priv->regs = of_iomap(node, 0); if (WARN_ON(!priv->regs)) { @@ -363,15 +432,23 @@ static int __init __plic_init(struct device_node *node, if (WARN_ON(!nr_irqs)) goto out_iounmap; + priv->nr_irqs = nr_irqs; + + priv->priority_reg = kcalloc(DIV_ROUND_UP(nr_irqs, + sizeof(unsigned long) * 8), + sizeof(unsigned long), GFP_KERNEL); + if (!priv->priority_reg) + goto out_free_priority_reg; + nr_contexts = of_irq_count(node); if (WARN_ON(!nr_contexts)) - goto out_iounmap; + goto out_free_priority_reg; error = -ENOMEM; priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1, &plic_irqdomain_ops, priv); if (WARN_ON(!priv->irqdomain)) - goto out_iounmap; + goto out_free_priority_reg; for (i = 0; i < nr_contexts; i++) { struct of_phandle_args parent; @@ -441,6 +518,11 @@ static int __init __plic_init(struct device_node *node, handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE + i * CONTEXT_ENABLE_SIZE; handler->priv = priv; + + handler->enable_reg = kcalloc(DIV_ROUND_UP(nr_irqs, 32), + 32, GFP_KERNEL); + if (!handler->enable_reg) + goto out_free_enable_reg; done: for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { plic_toggle(handler, hwirq, 0); @@ -461,11 +543,19 @@ static int __init __plic_init(struct device_node *node, plic_starting_cpu, plic_dying_cpu); plic_cpuhp_setup_done = true; } + plic_irq_pm_init(); pr_info("%pOFP: mapped %d interrupts with %d handlers for" " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); return 0; +out_free_enable_reg: + for_each_cpu(cpu, cpu_present_mask) { + handler = per_cpu_ptr(&plic_handlers, cpu); + kfree(handler->enable_reg); + } +out_free_priority_reg: + kfree(priv->priority_reg); out_iounmap: iounmap(priv->regs); out_free_priv: -- 2.39.0
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