Messages in this thread Patch in this message | | | From | Xingyu Wu <> | Subject | [PATCH v2 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks | Date | Tue, 21 Feb 2023 16:33:22 +0800 |
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Add DVP and HDMI TX pixel external fixed clocks and the rates are 74.25MHz and 297MHz.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 2 files changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index c2aa8946a0f1..27af817a55aa 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -86,6 +86,14 @@ &mclk_ext { clock-frequency = <12288000>; }; +&dvp_clk { + clock-frequency = <74250000>; +}; + +&hdmitx0_pixelclk { + clock-frequency = <297000000>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 005ead2624d4..a5e6fb3ad188 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -245,6 +245,18 @@ mclk_ext: mclk-ext-clock { #clock-cells = <0>; }; + dvp_clk: dvp-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; + + hdmitx0_pixelclk: hdmitx0-pixelclk-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; -- 2.25.1
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