Messages in this thread | | | Date | Wed, 15 Feb 2023 14:24:15 +0200 | From | Abel Vesa <> | Subject | Re: [PATCH] clk: imx: pll14xx: fix recalc_rate for negative kdiv |
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On 22-12-10 15:38:35, Kevin Groeneveld wrote: > kdiv is a signed 16 bit value in the DEV_CTL1 register. Commit > 53990cf9d5b4 ("clk: imx: pll14xx: consolidate rate calculation") changed > the kdiv variable from a short int to just int. When the value read from > the DIV_CTL1 register is assigned directly to an int the sign of the value > is lost resulting in incorrect results when the value is negative. Adding > a s16 cast to the register value fixes the issue. > > Fixes: 53990cf9d5b4 ("clk: imx: pll14xx: consolidate rate calculation") > Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Stephen, can you pick this up through fixes? > --- > drivers/clk/imx/clk-pll14xx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c > index 1d0f79e9c346..d12194d17b10 100644 > --- a/drivers/clk/imx/clk-pll14xx.c > +++ b/drivers/clk/imx/clk-pll14xx.c > @@ -254,7 +254,7 @@ static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, > > if (pll->type == PLL_1443X) { > pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); > - kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); > + kdiv = (s16)FIELD_GET(KDIV_MASK, pll_div_ctl1); > } else { > kdiv = 0; > } > -- > 2.17.1 >
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