Messages in this thread | | | Date | Mon, 13 Feb 2023 19:42:32 +0000 | From | Conor Dooley <> | Subject | Re: [PATCH v2 1/3] clk: k210: remove an implicit 64-bit division |
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On Sun, Feb 12, 2023 at 03:55:04PM -0500, Jesse Taube wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The K210 clock driver depends on SOC_CANAAN, which is only selectable > when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches > have been sent for its enabling. The kernel test robot reported this > implicit 64-bit division there. > > Replace the implicit division with an explicit one. > > Reported-by: kernel test robot <lkp@intel.com> > Link: https://lore.kernel.org/linux-riscv/202301201538.zNlqgE4L-lkp@intel.com/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
btw, you'll need to run get_maintainer.pl on this patch so that the k210 and clock maintainers are CCed.
It's also worth adding Damien Le Moal <damien.lemoal@wdc.com>
> --- > drivers/clk/clk-k210.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c > index 67a7cb3503c3..4eed667eddaf 100644 > --- a/drivers/clk/clk-k210.c > +++ b/drivers/clk/clk-k210.c > @@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw, > f = FIELD_GET(K210_PLL_CLKF, reg) + 1; > od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; > > - return (u64)parent_rate * f / (r * od); > + return div_u64((u64)parent_rate * f, r * od); > } > > static const struct clk_ops k210_pll_ops = { > -- > 2.39.0 > [unhandled content-type:application/pgp-signature] | |