Messages in this thread | | | From | Brandon Cheo Fusi <> | Subject | [RFC PATCH v2 0/3] Add support for reading D1 efuse speed bin | Date | Thu, 21 Dec 2023 11:10:10 +0100 |
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Hi everyone,
This series is an attempt to get feedback on decoding D1 efuse speed bins in the Sun50i H6 cpufreq driver, and turning the result into a meaningful value that selects voltage ranges in an OPP table.
I want to make sure I get this right before sending in a v3 of the D1 cpufreq support series here
https://lore.kernel.org/linux-sunxi/20231218110543.64044-1-fusibrandon13@gmail.com/T/#t
which is currently stuck at
https://lore.kernel.org/linux-sunxi/aad8302d-a015-44ee-ad11-1a4c6e00074c@sholland.org/
Changes in v2: - Make speed bin decoding generic in one patch and add D1 support in a separate patch - Fix OPP voltage ranges to avoid stability issues
Brandon Cheo Fusi (3): cpufreq: sun50i: Refactor speed bin decoding cpufreq: sun50i: Add support for D1's speed bin decoding riscv: dts: allwinner: Fill in OPPs
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 19 +++- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 89 +++++++++++++++---- 2 files changed, 89 insertions(+), 19 deletions(-)
-- 2.30.2
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