| Date | Tue, 19 Dec 2023 13:26:30 +0100 | Subject | Re: [PATCH v2 34/34] media: iris: add power management for encoder | From | Konrad Dybcio <> |
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On 18.12.2023 12:32, Dikshita Agarwal wrote: > Hardware specific power sequence include programming specific > sequence of registers. Implements this sequence for iris3. > > Also, implement iris3 Encoder specific calculation for clock > and bus bandwidth which depends on hardware configuration, > codec format, resolution and frame rate. > > Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com> > --- [...]
> +static const struct bw_info sm8550_bw_table_enc[] = { > + { 1944000, 1491000, 2693000 }, /* 3840x2160@60 */ > + { 972000, 765000, 1366000 }, /* 3840x2160@30 */ > + { 489600, 557000, 780000 }, /* 1920x1080@60 */ > + { 244800, 288000, 399000 }, /* 1920x1080@30 */ > +}; can this be calculated at runtime by chance?
Konrad
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