Messages in this thread Patch in this message | | | From | Yu Chien Peter Lin <> | Subject | [PATCH v4 10/13] dt-bindings: riscv: Add Andes PMU extension description | Date | Wed, 22 Nov 2023 20:12:32 +0800 |
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Document the ISA string for Andes Technology performance monitor extension which provides counter overflow interrupt and mode filtering mechanisms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Changes v2 -> v3: - New patch Changes v3 -> v4: - Include Conor's Acked-by --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 694efaea8fce..4e0066afc848 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -258,6 +258,13 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter overflow + and privilege mode filtering. For more details, see Counter Related + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + - const: xtheadpmu description: The T-Head performance monitor extension for counter overflow. For more -- 2.34.1
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