Messages in this thread Patch in this message | | | From | Yu Chien Peter Lin <> | Subject | [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string | Date | Wed, 22 Nov 2023 20:12:26 +0800 |
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Add "andestech,cpu-intc" compatible string to indicate that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt can be handled in supervisor mode:
- Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt
These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Updated commit message - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - Add const entry instead of enum (Suggested by Conor) --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d673..50307554478f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -100,7 +100,11 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true -- 2.34.1
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