Messages in this thread Patch in this message | | | From | Inochi Amaoto <> | Subject | [PATCH] riscv: dts: sophgo: remove address-cells from CV1800B intc node | Date | Mon, 13 Nov 2023 17:26:15 +0800 |
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A recent submission from Rob has added additionalProperties: false to the interrupt-controller child node of RISC-V cpus. But CV1800B does not follow this change and still uses #address-cells in its interrupt controller. As it has no child nodes, #address-cells is not needed and can be removed.
Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree") Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/
Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 - 1 file changed, 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index df40e87ee063..aec6401a467b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -34,7 +34,6 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; - #address-cells = <0>; #interrupt-cells = <1>; }; }; -- 2.42.1
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