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Subject[PATCH v3 0/3] clk: si5351: add option to adjust PLL without glitches
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From: Alvin Šipraga <alsi@bang-olufsen.dk>

This series intends to address a problem I had when using the Si5351A as
a runtime adjustable audio bit clock. The basic issue is that the driver
in its current form unconditionally resets the PLL whenever adjusting
its rate. But this reset causes an unwanted ~1.4 ms LOW signal glitch in
the clock output.

As a remedy, a new property is added to control the reset behaviour of
the PLLs more precisely. In the process I also converted the bindings to
YAML.

Changes:

v2 -> v3:

- address further comments from Rob:
- drop unnecessary refs and minItems
- simplify if conditions for chip variants
- ignore his comment about dropping '|', as line would be >80 columns
- move additionalProperties: false close to type: object
- define clocks/clock-names at top-level
- drop patch to dove-cubox dts per Krzysztof's comment - will send
separately
- collect Sebastian's Acked-by

v1 -> v2:

- address Rob's comments on the two dt-bindings patches
- new patch to correct the clock node names in the only upstream device
tree using si5351

Alvin Šipraga (3):
dt-bindings: clock: si5351: convert to yaml
dt-bindings: clock: si5351: add PLL reset mode property
clk: si5351: allow PLLs to be adjusted without reset

.../bindings/clock/silabs,si5351.txt | 126 --------
.../bindings/clock/silabs,si5351.yaml | 268 ++++++++++++++++++
drivers/clk/clk-si5351.c | 47 ++-
include/linux/platform_data/si5351.h | 2 +
4 files changed, 314 insertions(+), 129 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.txt
create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.yaml

--
2.42.0

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