Messages in this thread | | | From | Manivannan Sadhasivam <> | Subject | [PATCH v2 0/1] PCI: qcom-ep: Fix the BAR size programming | Date | Wed, 25 Oct 2023 18:30:28 +0530 |
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Hello,
This series fixes the issue seen on Qcom EP platforms implementing the DWC core while setting the BAR size. Currently, whatever the BAR size getting programmed through pci_epc_set_bar() on the EP side is not reflected on the host side during enumeration.
Debugging that issue revealed that the DWC Spec mandates asserting the DBI CS2 register in addition to DBI CS while programming some read only and shadow registers. So on the Qcom EP platforms, the driver needs to assert DBI_CS2 in ELBI region before writing DBI2 registers and deassert it once done.
This is done by implementing the write_dbi2() callback exposed by the DWC core driver in the Qcom PCIe EP driver.
This series has been tested on Qcom SM8450 based development platform.
- Mani
Changes in v2:
- Switch to write_dbi2() callback as suggested by Sergey
Manivannan Sadhasivam (1): PCI: qcom-ep: Implement write_dbi2() callback for writing DBI2 registers properly
drivers/pci/controller/dwc/pcie-qcom-ep.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
-- 2.25.1
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