Messages in this thread Patch in this message | | | From | Ilkka Koskinen <> | Subject | [PATCH] arm64: perf: Don't disgard upper 32 bits from PMCEID0/1 registers | Date | Wed, 25 Oct 2023 13:08:15 -0700 |
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The upper 32 bits of PMCEID[n] registers are used to describe whether architectural and microarchitectural events in range 0x4000-0x401f exist. Due to disgarding the bits, the driver made the events invisible, even if they existed.
Fixes: df29ddf4f04b ("arm64: perf: Abstract system register accesses away") Reported-by: Carl Worth <carl@os.amperecomputing.com> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> --- arch/arm64/include/asm/arm_pmuv3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h index 18dc2fb3d7b7..3e92b7cb57a4 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -126,12 +126,12 @@ static inline void write_pmuserenr(u32 val) write_sysreg(val, pmuserenr_el0); } -static inline u32 read_pmceid0(void) +static inline u64 read_pmceid0(void) { return read_sysreg(pmceid0_el0); } -static inline u32 read_pmceid1(void) +static inline u64 read_pmceid1(void) { return read_sysreg(pmceid1_el0); } -- 2.41.0
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