lkml.org 
[lkml]   [2023]   [Oct]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Subject[PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during
Date
Current driver is supports up to 16 buses. The following code fixes 
to support up to 256 buses.

update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
region to detect 256 buses.

Update ecam size to 256MB in device tree binding example.

Remove unwanted code.

Thippeswamy Havalige (4):
PCI: xilinx-nwl: Remove unnecessary code which updates primary,
secondary and sub-ordinate bus numbers
dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
PCI: xilinx-nwl: Rename ECAM size default macro
PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses

.../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++---------------
2 files changed, 4 insertions(+), 16 deletions(-)

--
2.25.1

\
 
 \ /
  Last update: 2023-10-16 07:11    [W:0.071 / U:0.824 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site