Messages in this thread Patch in this message | | | From | Sebastian Fricke <> | Date | Thu, 12 Oct 2023 13:01:04 +0200 | Subject | [PATCH v13 6/8] media: dt-bindings: wave5: add Chips&Media 521c codec IP support |
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From: Robert Beckett <bob.beckett@collabora.com>
Add bindings for the chips&media wave5 codec driver
Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> --- .../devicetree/bindings/media/cnm,wave5.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/cnm,wave5.yaml b/Documentation/devicetree/bindings/media/cnm,wave5.yaml new file mode 100644 index 000000000000..b31d34aec05b --- /dev/null +++ b/Documentation/devicetree/bindings/media/cnm,wave5.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cnm,wave5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chips&Media Wave 5 Series multi-standard codec IP + +maintainers: + - Nas Chung <nas.chung@chipsnmedia.com> + - Jackson Lee <jackson.lee@chipsnmedia.com> + +description: + The Chips&Media WAVE codec IP is a multi format video encoder/decoder + +properties: + compatible: + enum: + - cnm,cm521c-vpu + + reg: + maxItems: 1 + + clocks: + items: + - description: VCODEC clock + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The VPU uses the SRAM to store some of the reference data instead of + storing it on DMA memory. It is mainly used for the purpose of reducing + bandwidth. + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + vpu: video-codec@12345678 { + compatible = "cnm,cm521c-vpu"; + reg = <0x12345678 0x1000>; + clocks = <&clks 42>; + interrupts = <42>; + sram = <&sram>; + }; -- 2.25.1
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