Messages in this thread | | | Date | Thu, 12 Oct 2023 09:08:05 +0200 | From | Miquel Raynal <> | Subject | Re: [PATCH v2 2/4] mtd: rawnand: NAND controller write protect |
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Hi dregan@mail.com,
dregan@mail.com wrote on Thu, 12 Oct 2023 02:41:10 +0200:
> Allow NAND controller to be responsible for write protect pin > handling during fast path and exec_op destructive operation > when controller_wp flag is set. > > Signed-off-by: David Regan <dregan@mail.com> > > --- > > Changes in v2: none > --- > drivers/mtd/nand/raw/nand_base.c | 4 ++++ > include/linux/mtd/rawnand.h | 2 ++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c > index 47cc2c35153b..38ed0ced5b8e 100644 > --- a/drivers/mtd/nand/raw/nand_base.c > +++ b/drivers/mtd/nand/raw/nand_base.c > @@ -367,6 +367,10 @@ static int nand_check_wp(struct nand_chip *chip) > if (chip->options & NAND_BROKEN_XD) > return 0; > > + /* controller responsible for NAND write protect */ > + if (chip->controller->controller_wp) > + return 0; > + > /* Check the WP bit */ > ret = nand_status_op(chip, &status); > if (ret) > diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h > index 31aceda8616c..f03b9d7f48b8 100644 > --- a/include/linux/mtd/rawnand.h > +++ b/include/linux/mtd/rawnand.h > @@ -1111,6 +1111,7 @@ struct nand_controller_ops { > * the bus without restarting an entire read operation nor > * changing the column. > * @supported_op.cont_read: The controller supports sequential cache reads. > + * @controller_wp: controller responsible for NAND write protect.
The controller is in charge of handling the WP pin
> */ > struct nand_controller { > struct mutex lock; > @@ -1119,6 +1120,7 @@ struct nand_controller { > unsigned int data_only_read: 1; > unsigned int cont_read: 1; > } supported_op; > + bool controller_wp; > }; > > static inline void nand_controller_init(struct nand_controller *nfc) > -- > 2.37.3 > >
Thanks, Miquèl
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