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Subject[PATCH v1 09/13] riscv: hwprobe: export Zhintntl ISA extension
Date
Export Zihintntl extension[1] through hwprobe.

[1] https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
Documentation/riscv/hwprobe.rst | 3 +++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_riscv.c | 1 +
3 files changed, 5 insertions(+)

diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 06f49a095f19..a577b1d72dff 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -131,6 +131,9 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
supported as defined in the RISC-V ISA manual.

+ * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
+ is supported as defined in the RISC-V ISA manual.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index c9016abf099e..3c4aa5d01f93 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -47,6 +47,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZVKT (1 << 21)
#define RISCV_HWPROBE_EXT_ZFH (1 << 22)
#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23)
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 24)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index da916981934b..ca17829f3e16 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -156,6 +156,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZBA);
CHECK_ISA_EXT(ZBB);
CHECK_ISA_EXT(ZBS);
+ CHECK_ISA_EXT(ZIHINTNTL);

if (has_vector()) {
CHECK_ISA_EXT(ZVBB);
--
2.42.0
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