Messages in this thread | | | Date | Tue, 10 Oct 2023 17:36:50 +0100 | From | Marc Zyngier <> | Subject | Re: [RFC PATCH 0/3] Add HiSilicon system timer driver |
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On Tue, 10 Oct 2023 13:30:30 +0100, Yicong Yang <yangyicong@huawei.com> wrote: > > From: Yicong Yang <yangyicong@hisilicon.com> > > HiSilicon system timer is a memory mapped platform timer compatible with > the arm's generic timer specification. The timer supports both SPI and > LPI interrupt and can be enumerated through ACPI DSDT table. Since the > timer is fully compatible with the spec, it can reuse most codes of the > arm_arch_timer driver. However since the arm_arch_timer driver only > supports GTDT and SPI interrupt, this series support the HiSilicon system > timer by: > > - refactor some of the arm_arch_timer codes and export the function to > register a arch memory timer by other drivers > - retrieve the IO memory and interrupt resource through DSDT in a separate > driver, then setup and register the clockevent device reuse the arm_arch_timer > function > > Using LPI for the timer is mentioned in BSA Spec section 3.8.1 (DEN0094C 1.0C).
This strikes me as pretty odd. LPIs are, by definition, *edge* triggered. The timer interrupt must be *level* triggered. So there must be some bridge in the middle that is going to regenerate edges on EOI, and that cannot be architectural.
What am I missing?
Thanks,
M.
-- Without deviation from the norm, progress is not possible.
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