Messages in this thread | | | From | Guo Ren <> | Date | Wed, 4 Jan 2023 16:48:24 +0800 | Subject | Re: [RFC PATCH 1/3] riscv: errata: cmo: add CMO macro variant with both VA and PA |
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Thx for the patch! It's nice.
Reviewed-by: Guo Ren <guoren@kernel.org>
On Wed, Jan 4, 2023 at 3:42 PM Icenowy Zheng <uwu@icenowy.me> wrote: > > The standardized Zicbom extension supports only VA, however there's some > vendor extensions (e.g. XtheadCmo) that can handle cache management > operations on PA directly, bypassing the TLB lookup. > > Add a CMO alternatives macro variant that come with both VA and PA > supplied, and the code can be patched to use either the VA or the PA at > runtime. In this case the codepath is now patched to use VA for Zicbom > and PA for XtheadCmo. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > --- > arch/riscv/include/asm/errata_list.h | 30 ++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 46adc1c9428f..bf80dd58145e 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -118,6 +118,9 @@ asm volatile(ALTERNATIVE( \ > #define THEAD_clean_A0 ".long 0x0255000b" > #define THEAD_flush_A0 ".long 0x0275000b" > #define THEAD_SYNC_S ".long 0x0190000b" > +#define THEAD_inval_PA_A0 ".long 0x02a5000b" > +#define THEAD_clean_PA_A0 ".long 0x0295000b" > +#define THEAD_flush_PA_A0 ".long 0x02b5000b" > > #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > asm volatile(ALTERNATIVE_2( \ > @@ -144,6 +147,33 @@ asm volatile(ALTERNATIVE_2( \ > "r"((unsigned long)(_start) + (_size)) \ > : "a0") > > +#define ALT_CMO_OP_VPA(_op, _vaddr, _paddr, _size, _cachesize) \ > +asm volatile(ALTERNATIVE_2( \ > + __nops(6), \ > + "mv a0, %1\n\t" \ > + "j 2f\n\t" \ > + "3:\n\t" \ > + "cbo." __stringify(_op) " (a0)\n\t" \ > + "add a0, a0, %0\n\t" \ > + "2:\n\t" \ > + "bltu a0, %2, 3b\n\t" \ > + "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ > + "mv a0, %3\n\t" \ > + "j 2f\n\t" \ > + "3:\n\t" \ > + THEAD_##_op##_PA_A0 "\n\t" \ > + "add a0, a0, %0\n\t" \ > + "2:\n\t" \ > + "bltu a0, %4, 3b\n\t" \ > + THEAD_SYNC_S, THEAD_VENDOR_ID, \ > + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ > + : : "r"(_cachesize), \ > + "r"((unsigned long)(_vaddr) & ~((_cachesize) - 1UL)), \ > + "r"((unsigned long)(_vaddr) + (_size)), \ > + "r"((unsigned long)(_paddr) & ~((_cachesize) - 1UL)), \ > + "r"((unsigned long)(_paddr) + (_size)) \ > + : "a0") > + > #define THEAD_C9XX_RV_IRQ_PMU 17 > #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 > > -- > 2.38.1 >
-- Best Regards Guo Ren
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