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Subject[PATCH v1] riscv: support arch_has_hw_pte_young()
The arch_has_hw_pte_young() is false for riscv by default. If it's
false, page table walk is almost skipped for MGLRU reclaim. And it
will also cause useless step in __wp_page_copy_user().

RISC-V Privileged Book says that riscv have two schemes to manage A
and D bit.

So add a config for selecting, the default is true. For simple
implementation riscv CPU which just generate page fault, unselect it.

Signed-off-by: Jinyu Tang <>
arch/riscv/Kconfig | 10 ++++++++++
arch/riscv/include/asm/pgtable.h | 7 +++++++
2 files changed, 17 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index e2b656043abf..17c82885549c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -180,6 +180,16 @@ config PAGE_OFFSET
default 0x80000000 if 64BIT && !MMU
default 0xff60000000000000 if 64BIT

+ bool "Hardware Set PTE Access Bit"
+ default y
+ help
+ Select if hardware set A bit when PTE is accessed. The default is
+ 'Y', because most RISC-V CPU hardware can manage A and D bit.
+ But RISC-V may have simple implementation that do not support
+ hardware set A bit but only generate page fault, for that case just
+ unselect it.
depends on KASAN_GENERIC
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 4eba9a98d0e3..1db54ab4e1ba 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -532,6 +532,13 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
return ptep_test_and_clear_young(vma, address, ptep);
+#define arch_has_hw_pte_young arch_has_hw_pte_young
+static inline bool arch_has_hw_pte_young(void)
+ return true;

#define pgprot_noncached pgprot_noncached
static inline pgprot_t pgprot_noncached(pgprot_t _prot)
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