Messages in this thread | | | Date | Wed, 18 Jan 2023 06:26:51 +0200 | Subject | Re: [PATCH v3 5/8] phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets | From | Dmitry Baryshkov <> |
| |
On 18/01/2023 02:53, Abel Vesa wrote: > The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for > PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated > header file. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + > .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 +++++++++++++++++++ > 2 files changed, 24 insertions(+) > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-- With best wishes Dmitry
| |