Messages in this thread | | | Date | Wed, 18 Jan 2023 06:25:06 +0200 | Subject | Re: [PATCH v3 4/8] phy: qcom-qmp: pcs-pcie: Add v6 register offsets | From | Dmitry Baryshkov <> |
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On 18/01/2023 02:53, Abel Vesa wrote: > The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, > UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated > header file. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + > drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 +++++++++++++++ > 2 files changed, 16 insertions(+) > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-- With best wishes Dmitry
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