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SubjectRe: NXP imx6ull nonalignment buffer question
Hi

On Fri, Jan 13, 2023 at 4:30 AM Bough Chen <haibo.chen@nxp.com> wrote:
>
> > -----Original Message-----
> > From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> > Sent: 2023年1月9日 21:02
> > To: Bough Chen <haibo.chen@nxp.com>; Shawn Guo <shawnguo@kernel.org>;
> > Fabio Estevam <festevam@gmail.com>; LKML <linux-kernel@vger.kernel.org>
> > Cc: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>;
> > linux-mmc@vger.kernel.org; Ulf Hansson <ulf.hansson@linaro.org>
> > Subject: NXP imx6ull nonalignment buffer question
> >
> > Hi Haibo
> >
> > Working on imx6ulz design and found that if I send a sdio packet using the
> > sdio_writesb the adma driver tries to handle it with two dma descriptors. The
> > first one filled with the bytes up to 3 to cover the misalign and then another
> > buffer descriptor
> >
> > offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
> > SDHCI_ADMA2_MASK;
> > if (offset) {
> > if (data->flags & MMC_DATA_WRITE) {
> > buffer = sdhci_kmap_atomic(sg);
> > memcpy(align, buffer, offset);
> > sdhci_kunmap_atomic(buffer);
> > }
> >
> > /* tran, valid */
> > __sdhci_adma_write_desc(host, &desc,
> > align_addr,
> > offset,
> > ADMA2_TRAN_VALID);
> >
> > BUG_ON(offset > 65536);
> >
> > align += SDHCI_ADMA2_ALIGN;
> > align_addr += SDHCI_ADMA2_ALIGN;
> >
> > addr += offset;
> > len -= offset;
> > }
> >
> > In 48.7.4 Data Length Setting
> > For either ADMA (ADMA1 or ADMA2) transfer, the data in the data buffer must
> > be word aligned, so the data length set in the descriptor must be a multiple of 4.
> > I have noticed that this code does not work as expected.
>
> Hi Michael,
>
> My understanding is: for the sentence " the data in the data buffer must be word aligned", this means the start address of the data must be word aligned, but not limit the data length.
>

Ok. My specific problem is that this seems not working on imx6ulz, I
found the problem working on a wifi chipset, if the request gets split
for no-alignment
of the data in two dma descriptors, the chipset does not reply to me.
Anyway, I will retest it with the upstream kernel again. I will check
better and I will follow up if any more question

Thank you

> Best Regards
> Haibo Chen
> >
> > Did you have any feedback?
> >
> > Michael

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