Messages in this thread | | | Date | Fri, 2 Sep 2022 11:50:05 +0200 | From | Andrew Jones <> | Subject | Re: [PATCH 3/4] riscv: use BIT macros in t-head errata init |
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On Fri, Sep 02, 2022 at 12:27:43AM +0200, Heiko Stuebner wrote: > Using the appropriate BIT macro makes the code better readable. > > Suggested-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > arch/riscv/errata/thead/errata.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c > index bffa711aaf64..a6f4bd8ccf3f 100644 > --- a/arch/riscv/errata/thead/errata.c > +++ b/arch/riscv/errata/thead/errata.c > @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage, > u32 cpu_req_errata = 0; > > if (errata_probe_pbmt(stage, archid, impid)) > - cpu_req_errata |= (1U << ERRATA_THEAD_PBMT); > + cpu_req_errata |= BIT(ERRATA_THEAD_PBMT); > > if (errata_probe_cmo(stage, archid, impid)) > - cpu_req_errata |= (1U << ERRATA_THEAD_CMO); > + cpu_req_errata |= BIT(ERRATA_THEAD_CMO); > > return cpu_req_errata; > } > -- > 2.35.1 >
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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