Messages in this thread Patch in this message | | | From | Andy Shevchenko <> | Subject | [PATCH v1 03/17] pinctrl: cy8c95x0: Allow most of the registers to be cached | Date | Fri, 2 Sep 2022 21:26:36 +0300 |
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It's unclear why many of static registers were marked as volatile. They are pretty much bidirectional and static in a sense that written value is kept there until a new write or chip reset. Drop those registers from the list to allow them to be cached.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- drivers/pinctrl/pinctrl-cy8c95x0.c | 11 ----------- 1 file changed, 11 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 521acfdeef38..5ef772d29a36 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -303,17 +303,6 @@ static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) switch (reg) { case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): - case CY8C95X0_INTMASK: - case CY8C95X0_INVERT: - case CY8C95X0_PWMSEL: - case CY8C95X0_DIRECTION: - case CY8C95X0_DRV_PU: - case CY8C95X0_DRV_PD: - case CY8C95X0_DRV_ODH: - case CY8C95X0_DRV_ODL: - case CY8C95X0_DRV_PP_FAST: - case CY8C95X0_DRV_PP_SLOW: - case CY8C95X0_DRV_HIZ: return true; } -- 2.35.1
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