Messages in this thread Patch in this message | | | From | Siddharth Vadapalli <> | Subject | [PATCH 4/6] phy: ti: gmii-sel: Enable SGMII mode configuration for J721E | Date | Wed, 14 Sep 2022 15:09:09 +0530 |
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CPSW9G ports on J721E support SGMII mode. Add SGMII mode to the extra_modes member of struct "phy_gmii_sel_cpsw9g_soc_j721e".
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- drivers/phy/ti/phy-gmii-sel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index fdb1a7db123d..13877d0d15e4 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -227,7 +227,7 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), }; static const struct of_device_id phy_gmii_sel_id_table[] = { -- 2.25.1
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