Messages in this thread | | | Date | Sun, 11 Sep 2022 09:06:52 -0700 (PDT) | From | matthew.gerlach@linux ... | Subject | Re: [PATCH v1 1/5] Documentation: fpga: dfl: Add documentation for DFHv1 |
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On Sun, 11 Sep 2022, Xu Yilun wrote:
> On 2022-09-06 at 12:04:22 -0700, matthew.gerlach@linux.intel.com wrote: >> From: Matthew Gerlach <matthew.gerlach@linux.intel.com> >> >> Add documentation describing the extentions provided by Version >> 1 of the Device Feature Header (DFHv1). >> >> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> >> --- >> Documentation/fpga/dfl.rst | 24 ++++++++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> >> diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst >> index 15b670926084..31699b89781e 100644 >> --- a/Documentation/fpga/dfl.rst >> +++ b/Documentation/fpga/dfl.rst >> @@ -561,6 +561,30 @@ new DFL feature via UIO direct access, its feature id should be added to the >> driver's id_table. >> >> >> +Extending the Device Feature Header - DFHv1 >> +=========================================== >> +The current 8 bytes of the Device Feature Header, hereafter referred to as >> +to DFHv0, provide very little opportunity for the hardware to describe itself >> +to software. Version 1 of the Device Feature Header (DFHv1) is being introduced >> +to provide increased flexibility and extensibility to hardware designs using >> +Device Feature Lists. The list below describes some of the goals behind the >> +changes in DFHv1: >> + >> +* Provide a standardized mechanism for features to describe >> + parameters/capabilities to software. >> +* Standardize the use of a GUID for all DFHv1 types. >> +* Decouple the location of the DFH from the register space of the feature itself. >> + >> +Modeled after PCI Capabilities, DFHv1 Parameters provide a mechanism to associate >> +a list of parameter values to a particular feature. >> + >> +With DFHv0, not all features types contained a GUID. DFHv1 makes the GUILD standard >> +across all types. >> + >> +With DFHv0, the register map of a given feature is located immediately following >> +the DFHv0 in the memory space. With DFHv1, the location of the feature register >> +map can be specified as an offset to the DFHv1 or as an absolute address. > > Could you make a table or diagram to describe the data structure layout of DFHv1 > extention. > > Thanks, > Yilun
I was hoping that the actual macro definitions would be sufficient, but I will look into making a table.
Matthew Gerlach
> >> + >> Open discussion >> =============== >> FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration >> -- >> 2.25.1 >> >
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