Messages in this thread | | | Date | Thu, 1 Sep 2022 11:10:49 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH v2 8/9] perf/x86/intel: Shadow MSR_ARCH_PERFMON_FIXED_CTR_CTRL |
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On Wed, Aug 31, 2022 at 09:52:19AM -0400, Liang, Kan wrote: > > > On 2022-08-29 6:10 a.m., Peter Zijlstra wrote: > > Less RDMSR is more better. > > I had an RFC patch which does a further step to move the fixed > control register write to right before the entire PMU re-enabling, which > could also save some writes if there are several fixed counters enabled. > https://lore.kernel.org/lkml/20220804140729.2951259-1-kan.liang@linux.intel.com/ > > Do you have any comments for the RFC patch? >
Oh, I like that better, let me just replace my patch with that.
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