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    Subject[PATCH v2 8/9] perf/x86/intel: Shadow MSR_ARCH_PERFMON_FIXED_CTR_CTRL
    Less RDMSR is more better.

    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    ---
    arch/x86/events/intel/core.c | 8 ++++++--
    1 file changed, 6 insertions(+), 2 deletions(-)

    --- a/arch/x86/events/intel/core.c
    +++ b/arch/x86/events/intel/core.c
    @@ -2405,6 +2405,8 @@ static inline void intel_clear_masks(str
    __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
    }

    +static DEFINE_PER_CPU(u64, intel_fixed_ctrl);
    +
    static void intel_pmu_disable_fixed(struct perf_event *event)
    {
    struct hw_perf_event *hwc = &event->hw;
    @@ -2426,8 +2428,9 @@ static void intel_pmu_disable_fixed(stru
    intel_clear_masks(event, idx);

    mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
    - rdmsrl(hwc->config_base, ctrl_val);
    + ctrl_val = this_cpu_read(intel_fixed_ctrl);
    ctrl_val &= ~mask;
    + this_cpu_write(intel_fixed_ctrl, ctrl_val);
    wrmsrl(hwc->config_base, ctrl_val);
    }

    @@ -2746,9 +2749,10 @@ static void intel_pmu_enable_fixed(struc
    mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
    }

    - rdmsrl(hwc->config_base, ctrl_val);
    + ctrl_val = this_cpu_read(intel_fixed_ctrl);
    ctrl_val &= ~mask;
    ctrl_val |= bits;
    + this_cpu_write(intel_fixed_ctrl, ctrl_val);
    wrmsrl(hwc->config_base, ctrl_val);
    }


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