Messages in this thread | | | Date | Sun, 7 Aug 2022 12:35:03 +0200 | From | Borislav Petkov <> | Subject | Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry |
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On Sun, Aug 07, 2022 at 12:02:41PM +0200, Ingo Molnar wrote: > * Borislav Petkov <bp@alien8.de> wrote: > > With the amount of logical cores ever increasing and how CPU packages > > (nodes, L3 sharing, you name it) get more and more complex topology, > > I'd say the 2 insns to show the CPU number in every exception is a good > > thing to do. > > We can show it - I'm arguing against extracting it too early, which costs
Not early - more correct. We can say which CPU executed the exception handler *exactly*. Not which CPU executed the exception handler *maybe*.
> us 2 instructions in the exception fast path
2 insns? They don't matter at all. FWIW, they'll pull in the per-CPU cacheline earlier which should be a net win later, for code which does smp_processor_id().
> - while in 99.999999999% of the cases we don't use that field at all ...
See my text above about the ever-increasing complexity of CPU topology.
Thx.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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