Messages in this thread | | | Date | Mon, 8 Aug 2022 13:03:24 +0200 | From | Ingo Molnar <> | Subject | Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry |
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* Ira Weiny <ira.weiny@intel.com> wrote:
> On Sun, Aug 07, 2022 at 12:35:03PM +0200, Borislav Petkov wrote: > > On Sun, Aug 07, 2022 at 12:02:41PM +0200, Ingo Molnar wrote: > > > * Borislav Petkov <bp@alien8.de> wrote: > > > > With the amount of logical cores ever increasing and how CPU packages > > > > (nodes, L3 sharing, you name it) get more and more complex topology, > > > > I'd say the 2 insns to show the CPU number in every exception is a good > > > > thing to do. > > > > > > We can show it - I'm arguing against extracting it too early, which costs > > > > Not early - more correct. We can say which CPU executed the exception > > handler *exactly*. Not which CPU executed the exception handler *maybe*. > > > > > us 2 instructions in the exception fast path > > > > 2 insns? They don't matter at all. FWIW, they'll pull in the per-CPU > > cacheline earlier which should be a net win later, for code which does > > smp_processor_id().
I'd like to hear what Andy Lutomirski thinks about the notion that "2 instructions don't matter at all" ...
Especially since it's now 4 instructions:
> I agree with Boris; however I feel that I have to mention that in patch > 3/5 you also have 1 instruction on each of entry and exit to push the > extra stack space. So all told it would cost 4 instructions.
... 4 instructions in the exception path is a non-trivial impact.
> Again, I don't believe this is too much overhead but I don't want people > to say it was not discussed.
Is it necessary to do this, what are the alternatives, can this overhead be avoided?
Thanks,
Ingo
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