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SubjectRE: [PATCH 0/4]Add afi config drivers support
Date
Hi Yilun,

Please find my response inline.

> -----Original Message-----
> From: Xu Yilun <yilun.xu@intel.com>
> Sent: Saturday, August 27, 2022 11:33 AM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> linus.walleij@linaro.org; nava.manne@xilinx.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> Subject: Re: [PATCH 0/4]Add afi config drivers support
>
> CAUTION: This message has originated from an External Source. Please use
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>
> On 2022-08-24 at 09:25:38 +0530, Nava kishore Manne wrote:
> > Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the
> > programmable
>
> Could you help explain what is PS?
>

The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.

Will add PS description in next version.

Regards,
Navakishore.

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