Messages in this thread | | | Subject | Re: [PATCH 1/4] net: mediatek: sgmii: fix powering up the SGMII phy | From | Paolo Abeni <> | Date | Tue, 23 Aug 2022 15:10:38 +0200 |
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Hello,
On Sun, 2022-08-21 at 00:45 +0200, Alexander Couzens wrote: > There are cases when the SGMII_PHYA_PWD register contains 0x9 which > prevents SGMII from working. The SGMII still shows link but no traffic > can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was > taken from a good working state of the SGMII interface.
do you have access to register documentation? what does 0x9 actually mean? is the '0' value based on just empirical evaluation?
Thanks!
Paolo
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