Messages in this thread Patch in this message | | | From | Alexander Couzens <> | Subject | [PATCH 4/4] net: mediatek: sgmii: set the speed according to the phy interface in AN | Date | Sun, 21 Aug 2022 00:45:38 +0200 |
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The non auto-negotiating code path is setting the correct speed for the interface. Ensure auto-negotiation code path is doing it as well.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu> --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c index aa69baf1a42f..75de2c73a048 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -21,13 +21,20 @@ static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs) } /* For SGMII interface mode */ -static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) +static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface) { unsigned int val; /* PHYA power down */ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); + /* Set SGMII phy speed */ + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); + val &= ~RG_PHY_SPEED_MASK; + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val |= RG_PHY_SPEED_3_125G; + regmap_write(mpcs->regmap, mpcs->ana_rgc3, val); + /* Setup the link timer and QPHY power up inside SGMIISYS */ regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, SGMII_LINK_TIMER_DEFAULT); @@ -100,7 +107,7 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode, if (interface != PHY_INTERFACE_MODE_SGMII) err = mtk_pcs_setup_mode_force(mpcs, interface); else if (phylink_autoneg_inband(mode)) - err = mtk_pcs_setup_mode_an(mpcs); + err = mtk_pcs_setup_mode_an(mpcs, interface); return err; } -- 2.35.1
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