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Subject[PATCH 05/11] spi: dw: define SPI_CTRLR0 register and its fields
Date
Synopsys SSI controllers supporting enhanced SPI mode of operation has
SPI Control Register at offset 0xf4 which controls the following:

CLK_STRETCH_EN: Enables clock stretching capability in SPI transfers.
In case of write, if the FIFO becomes empty DWC_ssi will stretch the
clock until FIFO has enough data to continue the transfer. In case of
read, if the receive FIFO becomes full DWC_ssi will stop the clock until
data has been read from the FIFO.

WAIT_CYCLES: Wait cycles in Dual/Quad/Octal mode between control frames
transmit and data reception.

INST_L: Dual/Quad/Octal mode instruction length in bits.

ADDR_L: defines Length of Address to be transmitted.

For now, we are only using 32bit Address length and 8 bit Instruction
length.

Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
---
drivers/spi/spi-dw.h | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index b8cc20e0deaa..a7a4637d6d32 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -63,6 +63,17 @@
#define DW_SPI_RX_SAMPLE_DLY 0xf0
#define DW_SPI_CS_OVERRIDE 0xf4

+/* Register offsets (Defined in DWC SSI 1.03a) */
+#define DW_HSSI_SPI_CTRLR0 0xf4
+
+/* Bit fields in SPI_CTRLR0 (Defined in DWC SSI 1.03a) */
+#define DW_HSSI_SPI_CTRLR0_CLK_STRETCH_EN BIT(30)
+#define DW_HSSI_SPI_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11)
+#define DW_HSSI_SPI_CTRLR0_INST_L_MASK GENMASK(9, 8)
+#define DW_HSSI_SPI_CTRLR0_INST_L8 0x2
+#define DW_HSSI_SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
+#define DW_HSSI_SPI_CTRLR0_ADDR_L32 0x8
+
/* Bit fields in CTRLR0 (DWC APB SSI) */
#define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0)
#define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16)
--
2.30.2
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