Messages in this thread | | | Date | Thu, 18 Aug 2022 10:36:48 -0600 | From | Rob Herring <> | Subject | Re: [PATCH v3 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible |
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On Wed, Aug 17, 2022 at 09:12:11PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > While "real" hardware might not use the compatible string "riscv,plic0" > it is present in the driver & QEMU uses it for automatically generated > virt machine dtbs. To avoid dt-validate problems with QEMU produced > dtbs, such as the following, add it to the binding. > > riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed: > 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic'] > 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] > 'sifive,plic-1.0.0' was expected > 'thead,c900-plic' was expected > riscv-virt.dtb: plic@c000000: '#address-cells' is a required property > > Reported-by: Rob Herring <robh@kernel.org> > Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ > 1 file changed, 5 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
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