Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Thu, 18 Aug 2022 16:55:58 +0200 | Subject | Re: [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list |
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On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. In preparation to add support for RZ/Five SoC add > the Andes AX45MP core to the list. > > More details about Andes AX45MP core can be found here: > [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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