Messages in this thread Patch in this message | | | From | Lad Prabhakar <> | Subject | [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list | Date | Mon, 15 Aug 2022 16:14:45 +0100 |
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The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. In preparation to add support for RZ/Five SoC add the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here: [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- v1->v2 * Included ack from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 2a1c5ae5b0aa..1681767790c5 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,6 +27,7 @@ properties: oneOf: - items: - enum: + - andestech,ax45mp - canaan,k210 - sifive,bullet0 - sifive,e5 -- 2.25.1
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