Messages in this thread | | | Date | Wed, 27 Jul 2022 14:07:50 +0200 | Subject | Re: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu | From | Krzysztof Kozlowski <> |
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On 27/07/2022 13:43, Anup Patel wrote: > We add an optional DT property riscv,timer-can-wake-cpu which if present > in CPU DT node then CPU timer is always powered-on and never loses context. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d632ac76532e..b60b64b4113a 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -78,6 +78,12 @@ properties: > - rv64imac > - rv64imafdc > > + riscv,timer-can-wake-cpu: > + type: boolean > + description: > + If present, the timer interrupt can wake up the CPU from > + suspend/idle state.
Isn't this a property of a timer, not CPU? IOW, your timer node should have "wakeup-source" property.
Now that's actual problem: why the RISC-V timer is bound to "riscv" compatible, not to dedicated timer node? How is it related to actual CPU (not SoC)?
Best regards, Krzysztof
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