Messages in this thread | | | From | Anup Patel <> | Date | Wed, 27 Jul 2022 17:59:59 +0530 | Subject | Re: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu |
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On Wed, Jul 27, 2022 at 5:48 PM Sudeep Holla <sudeep.holla@arm.com> wrote: > > On Wed, Jul 27, 2022 at 05:13:01PM +0530, Anup Patel wrote: > > We add an optional DT property riscv,timer-can-wake-cpu which if present > > in CPU DT node then CPU timer is always powered-on and never loses context. > > > > I don't have much idea on idle states on RISC-V but associating this > property in just CPU node seems like not so good idea. > > This will be applicable for all CPU idle states which means you > can't use this even if one of the deepest idle state switches off > the timer. > > We have local-timer-stop in each idle states node. IIRC RISC-V uses the > binding which is now not arm specific[0] and IIRC you moved the binding > yourself. Any reason why not can't be used and any specific reason for > needing this extra property.
Indeed, the "local-timer-stop" property should be used. I guess, Allwinner D1 should use this property in idle state and we should not unconditionally set CLOCK_EVT_FEAT_C3STOP in the timer driver.
@Samuel Holland Can you confirm that the "local-timer-stop" property works for Allwinner D1 ? If yes, then please send a patch to remove CLOCK_EVT_FEAT_C3STOP from timer driver.
Regards, Anup
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