Messages in this thread Patch in this message | | | From | Lad Prabhakar <> | Subject | [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically | Date | Tue, 26 Jul 2022 19:06:19 +0100 |
| |
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..ffa8f12c29af 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,17 +27,17 @@ properties: oneOf: - items: - enum: - - sifive,rocket0 + - canaan,k210 - sifive,bullet0 - sifive,e5 - sifive,e7 - sifive,e71 - - sifive,u74-mc - - sifive,u54 - - sifive,u74 + - sifive,rocket0 - sifive,u5 + - sifive,u54 - sifive,u7 - - canaan,k210 + - sifive,u74 + - sifive,u74-mc - const: riscv - items: - enum: -- 2.17.1
| |