Messages in this thread Patch in this message | | | From | Krishna chaitanya chundru <> | Subject | [PATCH v2 2/3] dt-bindings: pci: QCOM Adding sc7280 aggre0, aggre1 clocks | Date | Fri, 1 Jul 2022 21:41:38 +0530 |
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Adding aggre0 and aggre1 clock entries to PCIe node.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12..8f29bdd 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -423,8 +423,8 @@ allOf: then: properties: clocks: - minItems: 11 - maxItems: 11 + minItems: 13 + maxItems: 13 clock-names: items: - const: pipe # PIPE clock @@ -437,6 +437,8 @@ allOf: - const: bus_slave # Slave AXI clock - const: slave_q2a # Slave Q2A clock - const: tbu # PCIe TBU clock + - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock - const: ddrss_sf_tbu # PCIe SF TBU clock resets: maxItems: 1 -- 2.7.4
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