Messages in this thread | | | Subject | Re: [PATCH 4/4] riscv: implement cache-management errata for T-Head SoCs | From | Samuel Holland <> | Date | Tue, 28 Jun 2022 20:29:46 -0500 |
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On 6/19/22 3:32 PM, Heiko Stuebner wrote: > The T-Head C906 and C910 implement a scheme for handling > cache operations different from the generic Zicbom extension. > > Add an errata for it next to the generic dma coherency ops. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Thanks for the update!
Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org>
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