Messages in this thread | | | Date | Tue, 21 Jun 2022 15:37:39 -0500 | From | Bjorn Helgaas <> | Subject | Re: [PATCH V11 4/8] cxl/pci: Create PCI DOE mailbox's for memory devices |
| |
In subject, I assume you mean the plural "mailboxes", not the possessive "mailbox's".
On Fri, Jun 10, 2022 at 01:22:55PM -0700, ira.weiny@intel.com wrote: > From: Ira Weiny <ira.weiny@intel.com> > > DOE mailbox objects will be needed for various mailbox communications > with each memory device. > > Iterate each DOE mailbox capability and create PCI DOE mailbox objects > as found. > > It is not anticipated that this is the final resting place for the > iteration of the DOE devices. The support of ports may drive this code > into the pcie side. In this imagined architecture the CXL port driver
s/pcie/PCIe/ to match other usage below.
> would then query into the PCI device for the DOE mailbox array. > > For now this is good enough for the endpoints and the split is similar > to the envisioned architecture where getting the mailbox array is > separated from the various protocol needs. For example, it is not > anticipated that the CDAT code will need to move because it is only > needed by the cxl_ports. > > Likewise irq's are separated out in a similar design pattern to the > PCIe port driver. But a much simpler irq enabling flag is used and only > DOE interrupts are supported.
I don't know what the convention is or will be for drivers/cxl. In drivers/pci, we favor "IRQ" over "irq" in English text to go along with PCI, DOE, CDAT, etc.
Also makes "IRQs" intelligible where "irq's" looks a little funny because the usage isn't possessive and "irqs" isn't obviously a word or an acronym.
Bjorn
| |