lkml.org 
[lkml]   [2022]   [Jun]   [20]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRE: [PATCH v2 3/3] fpga: region: Add runtime PM support
Date
Ping!

> -----Original Message-----
> From: Nava kishore Manne <nava.manne@xilinx.com>
> Sent: Monday, May 23, 2022 7:15 PM
> To: mdf@kernel.org; hao.wu@intel.com; yilun.xu@intel.com;
> trix@redhat.com; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> Michal Simek <michals@xilinx.com>; Nava kishore Manne
> <navam@xilinx.com>; linux-fpga@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; git <git@xilinx.com>
> Subject: [PATCH v2 3/3] fpga: region: Add runtime PM support
>
> Add support to handle FPGA/PL power domain. With this patch, the PL
> power domain will be turned on before loading the bitstream into the
> targeted region and turned off while removing/unloading the bitstream from
> the targeted region using overlays. This can be achieved by adding the
> runtime PM support to the fpga regions.
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v2:
> - Updated commit message.
> - Updated runtime PM handling logic to fix the PM ref count
> imbalance issues.
>
> drivers/fpga/of-fpga-region.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
> index ae82532fc127..f14bb5916d97 100644
> --- a/drivers/fpga/of-fpga-region.c
> +++ b/drivers/fpga/of-fpga-region.c
> @@ -15,6 +15,7 @@
> #include <linux/of_platform.h>
> #include <linux/slab.h>
> #include <linux/spinlock.h>
> +#include <linux/pm_runtime.h>
>
> static const struct of_device_id fpga_region_of_match[] = {
> { .compatible = "fpga-region", },
> @@ -301,10 +302,17 @@ static int of_fpga_region_notify_pre_apply(struct
> fpga_region *region,
> return -EINVAL;
> }
>
> + ret = pm_runtime_resume_and_get(dev->parent);
> + if (ret < 0) {
> + fpga_image_info_free(info);
> + return ret;
> + }
> +
> region->info = info;
> ret = fpga_region_program_fpga(region);
> if (ret) {
> /* error; reject overlay */
> + pm_runtime_put_sync(dev->parent);
> fpga_image_info_free(info);
> region->info = NULL;
> }
> @@ -324,10 +332,13 @@ static int of_fpga_region_notify_pre_apply(struct
> fpga_region *region, static void of_fpga_region_notify_post_remove(struct
> fpga_region *region,
> struct of_overlay_notify_data
> *nd) {
> + struct device *dev = &region->dev;
> +
> fpga_bridges_disable(&region->bridge_list);
> fpga_bridges_put(&region->bridge_list);
> fpga_image_info_free(region->info);
> region->info = NULL;
> + pm_runtime_put_sync(dev->parent);
> }
>
> /**
> @@ -411,6 +422,8 @@ static int of_fpga_region_probe(struct
> platform_device *pdev)
> goto eprobe_mgr_put;
> }
>
> + pm_runtime_enable(&pdev->dev);
> +
> of_platform_populate(np, fpga_region_of_match, NULL, &region-
> >dev);
> platform_set_drvdata(pdev, region);
>
> @@ -430,6 +443,7 @@ static int of_fpga_region_remove(struct
> platform_device *pdev)
>
> fpga_region_unregister(region);
> fpga_mgr_put(mgr);
> + pm_runtime_disable(region->dev.parent);
>
> return 0;
> }
> --
> 2.25.1

\
 
 \ /
  Last update: 2022-06-20 07:38    [W:0.134 / U:0.368 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site