Messages in this thread | | | From | Samuel Holland <> | Subject | [PATCH v2 0/6] genirq/irqchip: RISC-V PLIC cleanup and optimization | Date | Thu, 16 Jun 2022 01:40:22 -0500 |
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This series removes the splinlocks and cpumask operations from the PLIC driver's hot path. To do that, it first makes the IRQ affinity mask behavior more consistent between uniprocessor and SMP configurations. (The Allwinner D1 is a uniprocessor SoC containing a PLIC.)
As far as I know, using the priority to mask interrupts is an intended usage and will work on all existing implementations. See [1] for more discussion.
A further optimization is to take advantage of the fact that multiple IRQs can be claimed at once. This allows removing the mask operations for oneshot IRQs -- i.e. the combination of IRQCHIP_ONESHOT_SAFE and IRQCHIP_EOI_THREADED, which is not currently supported. I will send this as a separate series, since it makes more invasive changes to the generic IRQ code.
[1]: https://lore.kernel.org/lkml/2b063917-17c8-0add-fadf-5aa42532fbbf@sholland.org/
Changes in v2: - New patch to prevent GENERIC_IRQ_IPI from being selected on !SMP
Samuel Holland (6): genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP genirq: GENERIC_IRQ_IPI depends on SMP genirq: Refactor accessors to use irq_data_get_affinity_mask genirq: Provide an IRQ affinity mask in non-SMP configs irqchip/sifive-plic: Make better use of the effective affinity mask irqchip/sifive-plic: Separate the enable and mask operations
arch/arm/mach-hisi/Kconfig | 2 +- drivers/irqchip/Kconfig | 19 +++++----- drivers/irqchip/irq-sifive-plic.c | 61 ++++++++++++++++--------------- include/linux/irq.h | 20 ++++++---- kernel/irq/Kconfig | 2 + 5 files changed, 57 insertions(+), 47 deletions(-)
-- 2.35.1
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