Messages in this thread | | | Date | Fri, 6 May 2022 13:54:40 +0800 | From | kernel test robot <> | Subject | [esmil:visionfive 50/55] drivers/soc/sifive/sifive_l2_cache.c:158:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? |
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Hi Emil,
First bad commit (maybe != root cause):
tree: https://github.com/esmil/linux visionfive head: f568ecc24aebec8ce1c59b86f2a85098675a4091 commit: d9e1bb9d10657e8b58ea1d59ef125e674d1a3cf5 [50/55] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs config: riscv-randconfig-r024-20220505 (https://download.01.org/0day-ci/archive/20220506/202205061336.GeLV3Aeo-lkp@intel.com/config) compiler: riscv32-linux-gcc (GCC) 11.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/esmil/linux/commit/d9e1bb9d10657e8b58ea1d59ef125e674d1a3cf5 git remote add esmil https://github.com/esmil/linux git fetch --no-tags esmil visionfive git checkout d9e1bb9d10657e8b58ea1d59ef125e674d1a3cf5 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/soc/sifive/
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/soc/sifive/sifive_l2_cache.c: In function 'sifive_l2_flush64_range': >> drivers/soc/sifive/sifive_l2_cache.c:158:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Werror=implicit-function-declaration] 158 | writeq(line, l2_base + SIFIVE_L2_FLUSH64); | ^~~~~~ | writeb cc1: some warnings being treated as errors
vim +158 drivers/soc/sifive/sifive_l2_cache.c
a967a289f16969 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 126 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 127 #ifdef CONFIG_SIFIVE_L2_FLUSH 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 128 void sifive_l2_flush64_range(unsigned long start, unsigned long len) 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 129 { 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 130 unsigned long line; 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 131 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 132 if(!l2_base) { 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 133 pr_warn("L2CACHE: base addr invalid, skipping flush\n"); 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 134 return; 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 135 } 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 136 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 137 /* TODO: if (len == 0), skipping flush or going on? */ 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 138 if(!len) { 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 139 pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start); 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 140 return; 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 141 } 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 142 9b74c210c71a83 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 143 len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN); 9b74c210c71a83 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 144 start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN); 9b74c210c71a83 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 145 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 146 /* make sure the address is in the range */ 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 147 if(start < CONFIG_SIFIVE_L2_FLUSH_START || 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 148 (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 149 CONFIG_SIFIVE_L2_FLUSH_SIZE)) { 0725139bb25fb2 drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21 150 WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n", 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 151 start, len); 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 152 return; 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 153 } 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 154 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 155 mb(); /* sync */ 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 156 for (line = start; line < start + len; 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 157 line += SIFIVE_L2_FLUSH64_LINE_LEN) { 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 @158 writeq(line, l2_base + SIFIVE_L2_FLUSH64); 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 159 mb(); 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 160 } 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 161 } 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 162 EXPORT_SYMBOL_GPL(sifive_l2_flush64_range); 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 #endif 7fa12d2f832a42 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 164
:::::: The code at line 158 was first introduced by commit :::::: 7fa12d2f832a42a37ff0d8f4dd7569cee4b0b82f sifive/sifive_l2_cache: Add sifive_l2_flush64_range function
:::::: TO: Tom <support@vamrs.com> :::::: CC: Emil Renner Berthing <kernel@esmil.dk>
-- 0-DAY CI Kernel Test Service https://01.org/lkp
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