Messages in this thread Patch in this message | | | From | Po-Kai Chi <> | Subject | [PATCH] riscv: Invalid instruction cache after copy the xol area | Date | Wed, 18 May 2022 16:17:53 +0800 |
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We need to invalid the relevant instruction cache after copying the xol area, to ensure the changes takes effect.
Signed-off-by: Po-Kai Chi <po-kai.chi@sifive.com> --- arch/riscv/kernel/probes/uprobes.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/uprobes.c index 7a057b5f0adc..9d52beeac73c 100644 --- a/arch/riscv/kernel/probes/uprobes.c +++ b/arch/riscv/kernel/probes/uprobes.c @@ -165,6 +165,7 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, /* Initialize the slot */ void *kaddr = kmap_atomic(page); void *dst = kaddr + (vaddr & ~PAGE_MASK); + unsigned long addr = (unsigned long)dst; memcpy(dst, src, len); @@ -177,10 +178,9 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, kunmap_atomic(kaddr); /* - * We probably need flush_icache_user_page() but it needs vma. - * This should work on most of architectures by default. If - * architecture needs to do something different it can define - * its own version of the function. + * Flush both I/D cache to ensure instruction modification + * takes effect. */ flush_dcache_page(page); + flush_icache_range(addr, addr + len); } -- 2.36.1
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