Messages in this thread Patch in this message | | | From | Juerg Haefliger <> | Subject | [PATCH v2 1/3] ARM: Kconfig: Fix indentation | Date | Wed, 18 May 2022 08:43:26 +0200 |
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The convention for indentation seems to be a single tab. Help text is further indented by an additional two whitespaces. Fix the lines that violate these rules.
Signed-off-by: Juerg Haefliger <juergh@canonical.com>
--- v2: Drop endif/endmenu trailing comments. --- arch/arm/Kconfig | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e8091e2d8a8..e93653709f07 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -973,14 +973,14 @@ config ARM_ERRATA_764369 in the diagnostic control register of the SCU. config ARM_ERRATA_775420 - bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" - depends on CPU_V7 - help - This option enables the workaround for the 775420 Cortex-A9 (r2p2, - r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance - operation aborts with MMU exception, it might cause the processor - to deadlock. This workaround puts DSB before executing ISB if - an abort may occur on cache maintenance. + bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 775420 Cortex-A9 (r2p2, + r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance + operation aborts with MMU exception, it might cause the processor + to deadlock. This workaround puts DSB before executing ISB if + an abort may occur on cache maintenance. config ARM_ERRATA_798181 bool "ARM errata: TLBI/DSB failure on Cortex-A15" -- 2.32.0
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