lkml.org 
[lkml]   [2022]   [May]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH v2] PCI: cadence: Clear FLR in device capabilities register
Date
On Mon, 15 Nov 2021 23:39:16 -0800, Parshuram Raju Thombare wrote:
> From: Parshuram Thombare <pthombar@cadence.com>
>
> Clear FLR (Function Level Reset) from device capabilities
> registers for all physical functions.
>
> During FLR, the Margining Lane Status and Margining Lane Control
> registers should not be reset, as per PCIe specification.
> However, the controller incorrectly resets these registers upon FLR.
> This causes PCISIG compliance FLR test to fail. Hence preventing
> all functions from advertising FLR support if flag quirk_disable_flr
> is set.
>
> [...]

Applied to pci/cadence, thanks!

[1/1] PCI: cadence: Clear FLR in device capabilities register
https://git.kernel.org/lpieralisi/pci/c/d3dbd4d862

Thanks,
Lorenzo

\
 
 \ /
  Last update: 2022-05-11 18:03    [W:0.335 / U:0.072 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site