Messages in this thread Patch in this message | | | From | Atish Patra <> | Subject | [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32 | Date | Wed, 11 May 2022 13:11:06 -0700 |
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Pass the upper half of the initial value of the counter correctly for RV32.
Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
Signed-off-by: Atish Patra <atishp@rivosinc.com> --- drivers/perf/riscv_pmu_sbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index a1317a483512..24cea59612be 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, max_period = riscv_pmu_ctr_get_width_mask(event); init_val = local64_read(&hwc->prev_count) & max_period; sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, 0, 0); + flag, init_val, init_val >> 32, 0); } ctr_ovf_mask = ctr_ovf_mask >> 1; idx++; -- 2.25.1
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